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Integrated Circuit Systems, Inc.
ICS95V842I
DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)
Recommended Application: 1:2 DDRI Clock Driver Product Description/Features: * Low skew, low jitter PLL clock driver * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs * With bypass mode mux * Operating frequency 60 to 220 MHz Switching Characteristics: * CYCLE - CYCLE jitter: <75ps * OUTPUT - OUTPUT skew: <60ps * Period jitter: 75ps * Half-Period jitter: 75ps
Pin Configuration
VDD2.5 DDRT0 DDRC0 GND CLK_INT CLK_INC AVDD AGND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND DDRC1 DDRT1 VDD2.5 FB_INC FB_INT FB_OUTT FB_OUTC
16 pin SSOP
Functionality
INPUTS GND GND 2.5V (nom) 2.5V (nom) L H L H H L H L L H L H H L H L OUTPUTS L H L H H L H L AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC PLL State Bypassed/Off Bypassed/Off On On
Block Diagram
FB_INT FB_INC CLK_INC CLK_INT
PLL
FB_OUTT FB_OUTC DDRT (1:0) DDRC (1:0)
AVDD
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ICS95V842
ICS95V842I
Pin Descriptions
PIN # PIN NAME PIN TYPE DESCRIPTION
1 2 3 4 5 6 7 8 9
VDD2.5 DDRT0 DDRC0 GND CLK_INT CLK_INC AVDD AGND FB_OUTC
PWR OUT OUT PWR IN IN PWR PWR OUT
Power supply, nominal 2.5V "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Ground pin. "True" reference clock input. "Complementary" reference clock input. 3.3V Analog Power pin for Core PLL Analog Ground pin for Core PLL Complement single-ended feedback output, dedicated external feedback. It switches at the same frequency as other DDR outputs. True single-ended feedback output, dedicated external feedback. It switches at the same frequency as other DDR outputs. True single-ended feedback input, provides feedback signal to internal PLL for synchronization with CLK_INT to eliminate phase error. Complement single-ended feedback input, provides feedback signal to internal PLL for synchronization with CLK_INT to eliminate phase error. Power supply, nominal 2.5V "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Ground pin.
10
FB_OUTT
OUT
11
FB_INT
IN
12 13 14 15 16
FB_INC VDD2.5 DDRT1 DDRC1 GND
IN PWR OUT OUT PWR
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ICS95V842I
Absolute Maximum Ratings
Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . . -0.5V to 3.6V Input clamp current: IIK (VI < 0 or VI > VDD) . . . . . . +/- 50mA Output clamp current: I OK (VO < 0 or VO > VDD) . . +/- 50mA Continuous output current: IO (VO = 0 to VDD) . . . . +/- 50mA Package thermal impedance, theta JA: DGG package +89C/ Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = -40C to +85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) SYMBOL MIN TYP PARAMETER CONDITIONS IIH VI = VDD or GND Input High Current 5 IIL VI = VDD or GND Input Low Current Operating Supply Current Output High Current Output Low Current High Impedance Output Current Input Clamp Voltage IDD2.5 IDDPD IOH IOL IOZ VIK VOH MAX 5 160 100 -18 26 10 -1.2 VDD - 0.1 1.7 0.1 0.6 3 3 V pF pF UNITS A A mA A mA mA A V V V
CL = 0pF, RL = CL = 0pF, RL = VDD = 2.3V, VOUT = 1V
VDD = 2.3V, VOUT = 1.2V VDD=2.7V, Vout=VDD or GND Iin = -18mA VDD = min to max, IOH = -1 mA VDD = 2.3V, IOH = -12 mA VDD = min to max IOL=1 mA VDD = 2.3V IOH=12 mA VI = VDD or GND VI = VDD or GND
High-level output voltage
Low-level output voltage
VOL
1 CIN Input Capacitance 1 COUT Output Capacitance 1 Guaranteed by design and characterization, not 100% tested in production.
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ICS95V842I
DC Electrical Characteristics
TA = -40C to +85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP 2.3 2.5 Supply Voltage V DDQ, AVDD CLK_INT, CLK_INC, FB_INC, 0.4 Low level input voltage V IL FB_INT CLK_INT, CLK_INC, FB_INC, 2.1 VDD/2 + 0.18 High level input voltage VIH FB_INT DC input signal voltage -0.3 VIN (note 1,2) CLK_INT, CLK_INC, FB_INC, Differential input signal 0.36 VID FB_INT voltage (note 3) CLK_INT, CLK_INC, FB_INC, Differential output voltage VOD 0.7 (note 3) FB_INT Output differential crossVOX V DD/2 - 0.15 voltage (note 4) Input differential crossVIX V DD/2 - 0.2 VDD/2 voltage (note 4) Operating free-air TA -40 temperature MAX 2.7 VDD/2 - 0.18 UNITS V V V V DD + 0.3 V DD + 0.6 V DD + 0.6 VDD/2 + 0.15 VDD/2 + 0.2 85 V V V V V C
Notes: 1 Unused inputs must be held high or low to prevent them from floating. 2 DC input signal voltage specifies the allowable DC excursion of differential input. 3 Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4 Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing.
Timing Requirements
TA = -40C to +85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX UNITS Max clock frequency 3 Application Frequency Range3 Input clock duty cycle CLK stabilization freqop freqApp dtin TSTAB 33 60 40 233 220 60 100 MHz MHz % s
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ICS95V842I
Switching Characteristics
TA = -40C to +85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Max clock frequency 3 Application Frequency Range3 Input clock duty cycle Input clock slew rate CLK stabilization Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Output clock slew rate Cycle to Cycle Jitter Static Phase Offset Output to Output Skew SYMBOL freqop freqApp dtin t sl(I) TSTAB tPLH1 tPHL1 ten tdis tjit (per) t jit(hper) tsl(o) tcyc -tcyc t(spo) tskew CLK_IN to any output CLK_IN to any output PD# to any output PD# to any output -75 -75 1 -75 -50 40 5 5 75 75 2.5 75 50 60 CONDITION MIN 40 60 40 1 TYP MAX 333 220 60 2 100 5.5 5.5 UNITS MHz MHz % v/ns s ns ns ns ns ps ps v/ns ps ps ps
Over the application frequency range
Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics are guaranteed for application frequency range. The PLL Locks over the Max Clock Frequency range, but the device doe not necessarily meet other timing parameters. 4. Does not include jitter.
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ICS95V842I
Parameter Measurement Information VDD V(CLKC)
R = 60
R = 60 VDD/2 V(CLKC) ICS95V842 GND Figure 1. IBIS Model Output Load VDD/2 ICS95V842 Z = 60 C = 14 pF -V DD/2 R = 10 Z = 50 SCOPE
R = 50 V(TT) Z = 60 R = 10 Z = 50
C = 14 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit
R = 50 V(TT)
YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) tc(n+1) Figure 3. Cycle-to-Cycle Jitter
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ICS95V842I
Parameter Measurement Information CLK_INC CLK_INT
FB_INC FB_INT
t( ) n
n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX # YX
YX, FB_OUTC YX, FB_OUTT t(SK_O) Figure 5. Output Skew
YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter
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ICS95V842I
Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT
t (hper_n) 1 fo t (hper_n+1)
t(jit_Hper) = t(jit_Hper_n) - 1 2xfO Figure 7. Half-Period Jitter
80%
80% VID , VOD
Clock Inputs and Outputs
20% Rise tsl Fall tsl
20%
Figure 8. Input and Output Slew Rates
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ICS95V842I
16-Lead, 150 mil SSOP (QSOP) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 1.35 1.75 .053 .069 A1 0.10 0.25 .004 .010 A2 -1.50 -.059 b 0.20 0.30 .008 .012 c 0.18 0.25 .007 .010 SEE VARIATIONS D SEE VARIATIONS E 5.80 6.20 .228 .244 E1 3.80 4.00 .150 .157 e 0.635 BASIC 0.025 BASIC L 0.40 1.27 .016 .050 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 ZD SEE VARIATIONS SEE VARIATIONS VARIATIONS N 16 D mm. MIN 4.80 MAX 5.00 ZD (Ref) 0.23 D (inch) MIN .189 MAX .197 ZD (Ref) .009
Reference Doc.: JEDEC Publication 95, MO-137
10-0032
Ordering Information
ICS95V842YFILF-T
Example:
ICS XXXX y F I LF - T
Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) I = Industrial Temperature Range Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type
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Prefix ICS = Standard Device
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